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CL-PS6700
Preliminary Data Book
FEATURES
s Direct interface to CL-PS7111 low-power microcontroller
-- Custom multiplexed address/data bus for low pin count -- Supports 13- and 18-MHz operating frequencies
Low-Power PC Card Controller for the CL-PS7111
OVERVIEW
The CL-PS6700 connects directly to a PC Card (PCMCIA) Release 2.01 socket and has a custom interface to the CL-PS7111 microcontroller. The CL-PS7111 can support up to two CL-PS6700 devices, which allows up to two PC Card sockets per system. Addresses and data are passed to the CL-PS6700 through 16 bits of the 32-bit Data bus (D[15:0]). The PC Card socket is effectively isolated by the CL-PS6700. Except for power and ground pins, the pins on the socket only connect to the rest of the system through the CL-PS6700.
s Fully compatible with PC Card (PCMCIA) Release 2.01 specification s One or two CL-PS6700s per system s Low power states
-- Operating (25 mW, typical) -- Idle -- Standby (virtually zero power drain)
s Support for PC Card hot insertion and removal s Read and write buffers s Support for 3.3- and 5-V PC Cards s Endian conversion s Supports the following PC Cards:
-- -- -- -- Memory-only card; flash, EPROM, or SRAM I/O card; modem and communications Cards configured as both I/O and memory DMA-capable cards (through software emulation)
s 100-pin VQFP package
(cont.)
CL-PS7111-to-CL-PS6700 Interface
5 V 3 V VPP VCC VPP
SYS_RES_L RESET_L EXPCLK NCS[4] WRITE PCLK PCE_L PTYPE I/O POWER = V3V_O
PCTL[2:0]
POWER MODULE
PCM_VS[2:1] PCM_CD[2:1] PCM_BVD[2:1] PCM_WP PCM_RDY I/O POWER = V5V_O PCM_WAIT PCM_RESET PCM_CE[2:1] PCM_REG_L PCM_OE_L PCM_WE_L PCM_IORD_L PCM_IOWR_L PCM_A[25:0]
CL-PS7111
NEINTN
PIRQ_L[1:0]
GPIO
PSLEEP_L
D[15:0]
MD[15:0]
CL-PS6700
PB[0]
PRDY
PC CARD SOCKET
PCM_D[15:0]
Version 1.0
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CL-PS6700
Low-Power PC Card Controller
OVERVIEW (cont.)
CL-PS7111-to-CL-PS6700 Interface
The PC Card interface requires a 26-bit address bus and a 16-bit data bus. The interface between the CL-PS6700 and CL-PS7111 consists of a 16-bit bus that carries the address and data information, and several control signals. This bus defines a two-clock address phase during which the 26-bit PC Card address and 6 control bits are transferred, and a one- or two-clock data phase during which one or four bytes of data are transferred. The data phase for reads can be deferred (for example, for a DMA access to the frame buffer of the CL-PS7111). If a write transfer is indicated, write data appears in the third clock phase. If a word write is indicated, write data also appears in the fourth clock phase. For read transfers, the CL-PS6700 drives the bus with read data during the first one or two clocks of the data phase. This interface bus is also shared by other memory devices and up to one additional CL-PS6700 device. The CL-PS7111 accesses the CL-PS6700 as a memory-mapped peripheral on the 16-bit memory bus. A Chip Enable signal (NCS[4]) from the CL-PS7111 selects one CL-PS6700 device for access to a particular PC Card socket. Another Chip Enable signal (NCS[5]) connects a second PC Card socket. The CL-PS6700 implements the low-level interface to the PC Card socket and provides voltage translation for mixed-voltage systems. The CL-PS6700 also provides the data buffer and interrupt controls for the PC Card. Transfers between the two devices can be either one or four bytes. The CL-PS6700 can be programmed to assemble/disassemble CL-PS7111 transfers to the width of the PC Card. The CL-PS6700 has read and write buffers that allow posting of both reads and writes. The read queue is single entry; the write FIFO can queue up to four CL-PS7111 transactions (up to 16 bytes).
Hot Insertion Support
The CL-PS6700 PC Card controller allows PC Cards to be inserted or removed while system power is on. The CL-PS7111 controller typically applies power to a PC Card socket after it has detected a properly inserted card. The device removes the power before the card is removed (that is, when the CPU detects that the card lock is deasserted). Since each card is isolated from the system by the associated CL-PS6700, insertion and removal of cards do not cause interference on the system buses.
Card Configuration and Access
After power-on or reset, a PC Card defaults to a memory-only card. The CL-PS7111 then reads the CIS of the card to determine the card type, access time, and so on, and configures the CL-PS6700 to access the card. Each PC Card's VCC and VPP pins are individually controlled by its associated CL-PS6700. The CL-PS7111 controls the power to a card by writing to the CL-PS6700 registers. The CL-PS6700 ensures that its signals to the sockets are in the proper state before applying or removing power. The CL-PS6700 device is available in an 100-pin VQFP package. The device can be used with both operating frequencies of the CL-PS7111 (13 and 18 MHz at 2.7 and 3.3 V).
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OVERVIEW
PRELIMINARY DATA BOOK v1.0
November 1997
CL-PS6700
Low-Power PC Card Controller
TABLE OF CONTENTS
CONVENTIONS ......................................................................................... 5 1. PIN INFORMATION.................................................................................... 7
1.1 100-Pin VQFP Pin Diagram ....................................................................................... 7 1.2 Pin Listings................................................................................................................. 8
2. PIN DESCRIPTIONS................................................................................ 10
2.1 CL-PS7111-to-CL-PS6700 Interface Signals........................................................... 10 2.1.1 Address/Data Bus Signals ............................................................................ 10 2.1.2 Access Control Signals................................................................................. 12 2.1.3 Interrupt and Abort Signals........................................................................... 13 2.1.4 Clock, Reset, and Sleep Signals .................................................................. 13 2.2 PC Card Interface Signals........................................................................................ 14 2.2.1 Address and Data Signals ............................................................................ 14 2.2.2 Access Control Signals................................................................................. 14 2.2.3 Additional Control for I/O Signals.................................................................. 16 2.2.4 Card Detect and Battery Status Signals ....................................................... 16 2.2.5 Card Voltages and Reset Signals ................................................................. 17 2.3 Power and Ground Pins ........................................................................................... 17
3. FUNCTIONAL DESCRIPTION................................................................. 18
3.1 PC Card (PCMCIA) Interface ................................................................................... 18 3.1.1 PC Card Types.............................................................................................. 18 3.1.2 PC Card Address/Data Bus .......................................................................... 18 3.1.3 PC Card Address Spaces and DMA............................................................. 18 3.1.4 Byte Assembly/Disassembly and Queueing ................................................. 19 3.1.5 Card Configuration........................................................................................ 19 3.1.6 Hot Insertion Support ................................................................................... 19 3.2 Power States ............................................................................................................ 20 3.2.1 Active State................................................................................................... 20 3.2.2 Idle State....................................................................................................... 20 3.2.3 Standby State ............................................................................................... 20
4. REGISTERS ............................................................................................. 21
4.1 Register Addresses.................................................................................................. 21 4.2 Interrupt Structure .................................................................................................... 23 4.3 Power Management Registers ................................................................................. 24 4.3.1 Power Management Register (0X0C002800) ............................................... 24 4.3.2 Card Power Control Register (0X0C002C00) ............................................... 25 4.4 System Interface Registers ...................................................................................... 26 4.4.1 System Interface Configuration Register (0X0C002000).............................. 26 4.4.2 DMA Control Register (0X0C004000) .......................................................... 27 4.4.3 Device Information Register (0X0C004400) ................................................. 27 4.5 Card Interface Registers .......................................................................................... 28 4.5.1 Card Interface Configuration Register (0X0C002400).................................. 28 4.5.2 Card Interface Timing Register 0A (0X0C003000) ....................................... 29 4.5.3 Card Interface Timing Register 0B (0X0C003400) ....................................... 29 4.5.4 Card Interface Timing Register 1A (0X0C003800) ....................................... 30 4.5.5 Card Interface Timing Register 1B (0X0C003C00)....................................... 30 CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
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PRELIMINARY DATA BOOK v1.0
TABLE OF CONTENTS
3
CL-PS6700
Low-Power PC Card Controller
4.6 I/O Properties........................................................................................................... 31
5. ELECTRICAL SPECIFICATIONS............................................................ 33
5.1 Bus Timing -- System Bus ...................................................................................... 35 5.2 Bus Operations ........................................................................................................ 38
6. PACKAGE SPECIFICATIONS ................................................................. 43 7. ORDERING INFORMATION .................................................................... 44 BIT INDEX................................................................................................ 45 INDEX....................................................................................................... 46
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TABLE OF CONTENTS
PRELIMINARY DATA BOOK v1.0
November 1997
CL-PS6700
Low-Power PC Card Controller
CONVENTIONS
This section presents conventions, abbreviations and acronyms, pin type abbreviations, and units of measure used in this data book.
Abbreviations and Acronyms
Acronym or Definition Abbreviation
CIS CMOS CPU DC DMA EPROM FIFO GPIO LSB MSB RAM ROM SRAM VQFP card information structure complementary metal-oxide semiconductor central processing unit direct current direct-memory access erasable/programmable read-only memory first in/first out general-purpose I/O least-significant bit most-significant bit random-access memory read-only memory static random-access memory very-tight-pitch quad flat pack
Pin Type Abbreviations
Abbreviation
I O I/O OD-O
Type
Input Output Input/output Open-drain output
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PRELIMINARY DATA BOOK v1.0
CONVENTIONS
5
CL-PS6700
Low-Power PC Card Controller
Units of Measure
Symbol
C Hz Kbyte k A s Mbyte MHz mA ms mW ns V W
Units of Measure
degree Celsius hertz (cycle per second) kilobyte (1,024 bytes) kilohm microampere microsecond (1,000 nanoseconds) megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) milliampere millisecond (1,000 microseconds) milliwatt nanosecond volt microwatt
OTHER CONVENTIONS
Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For example, 14h and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text. For example, `11' is a binary number. Numbers not indicated by an h or single quotation marks are decimal. The use of `tbd' indicates values that are `to be determined', `n/a' designates `not available', and `n/c' indicates a pin that is a `no connect'.
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CONVENTIONS
PRELIMINARY DATA BOOK v1.0
November 1997
CL-PS6700
Low-Power PC Card Controller
1. PIN INFORMATION
1.1 100-Pin VQFP Pin Diagram
PCM_VS[1] [I/O]
PCM_VS[2] [I/O]
PCM_BVD[1] [I]
PCM_BVD[2] [I]
PCM_D[10] [O]
PCM_CD[1] [I]
PCM_CD[2] [I]
PCM_D[2] [O]
PCM_D[1] [O]
PCM_D[8] [O]
PCM_D[9] [O]
PCM_D[0] [O]
PCM_RESET [O] 77
PCM_WAIT [I]
PCM_A[0] [O]
PCM_A[1] [O]
PCM_A[2] [O]
PCM_A[3] [O]
100
92
91
90
99
98
97
96
95
94
93
89
88
87
86
84
83
82
81
80
79
78
PCM_A[4] [O]
PSLEEP_L [I]
PCM_WP [I]
PCTL[0] [O]
PCTL[1] [O]
PCTL[2] [O]
RESET_L [I] PIRQ_L[0] [O] PIRQ_L[1] [O] MD[0] [I/O] MD[1] [I/O] MD[2] [I/O] VSS_O MD[3][I/O] V3V_O MD[4] [I/O] MD[5] [I/O] V3V_CORE MD[6] [I/O] MD[7] [I/O] VSS_CORE PCLK [I] MD[8] [I/O] MD[9] [I/O] MD[10] [I/O] VSS_O MD[11] [I/O] V3V_O MD[12] [I/O] MD[13] [I/O] MD[14] [I/O]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
85
76
PCM_A[5] [O]
75 74 73 72 71 70 69 68 67 66
PCM_A[6] [O] VSS_O PCM_A[7] [O] V5V_O PCM_A[25] [O] VDD_HI PCM_A[24] [O] PCM_A[12] [O] PCM_A[23] [O] PCM_A[15] [O] VSS_CORE PCM_A[22] [O] V3V_CORE PCM_A[16] [O] PCM_A[21] [O] PCM_RDY [I/O] PCM_A[20] [O] PCM_WE_L [O] PCM_A[19] [O] PCM_A[14] [O] PCM_A[18] [O] PCM_A[13] [O] PCM_A[17] [O] PCM_A[8] [O] PCM_IOWR_L [O]
CL-PS6700
100-Pin VQFP
65 64 63 62 61 60 59 58
19 20 21 22 23 24 25
57 56 55 54 53 52 51 45 46 47 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 48 49 PCM_IORD_L [O] 50 PCM_A[9] [O]
PCM_REG_L [O]
PCM_D[11] [O]
PCM_D[12] [O]
PCM_D[13] [O]
PCM_D[14] [O]
PCM_CE[1] [O]
PCM_D[15] [O]
PCM_A[10] [O]
PCM_CE[2] [O]
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PCM_OE_L [O]
PCM_A[11] [O]
PDREQ_L [O]
PTYPE [I]
PCM_D[3] [O]
PCM_D[4] [O]
PCM_D[5] [O]
PCM_D[6] [O]
PCM_D[7] [O]
PCE_L [I]
VSS_O
MD[15] [I/O]
PRDY [O]
V5V_O
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PIN INFORMATION
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CL-PS6700
Low-Power PC Card Controller
1.2 Pin Listings
Table 1-1 lists the pins of the CL-PS6700 in alphabetical order. Table 1-2 lists the pins in numerical order. Table 1-1.
Signal Name
MD[0] MD[1] MD[2] MD[3] MD[4] MD[5] MD[6] MD[7] MD[8] MD[9] MD[10] MD[11] MD[12] MD[13] MD[14] MD[15] PCE_L PCLK PCM_A[0] PCM_A[1] PCM_A[2] PCM_A[3] PCM_A[4] PCM_A[5] PCM_A[6]
Alphabetical Listing
Pin No.
4 5 6 8 10 11 13 14 17 18 19 21 23 24 25 26 30 16 84 82 81 80 78 76 75
Type
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O O O O O O
Signal Name
PCM_A[7] PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] PCM_A[12] PCM_A[13] PCM_A[14] PCM_A[15] PCM_A[16] PCM_A[17] PCM_A[18] PCM_A[19] PCM_A[20] PCM_A[21] PCM_A[22] PCM_A[23] PCM_A[24] PCM_A[25] PCM_BVD[1] PCM_BVD[2] PCM_CD[1] PCM_CD[2] PCM_CE[1] PCM_CE[2]
Pin No.
73 52 50 44 48 68 54 56 66 62 53 55 57 59 61 64 67 69 71 85 83 94 93 42 45
Type
O O O O O O O O O O O O O O O O O O O I I I I O O
Signal Name
PCM_D[0] PCM_D[1] PCM_D[2] PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] PCM_D[8] PCM_D[9] PCM_D[10] PCM_D[11] PCM_D[12] PCM_D[13] PCM_D[14] PCM_D[15] PCM_IORD_L PCM_IOWR_L PCM_OE_L PCM_RDY PCM_REG_L PCM_RESET PCM_VS[1] PCM_VS[2] PCM_WAIT
Pin No.
86 88 90 32 33 35 37 39 87 89 91 34 36 38 40 43 49 51 47 60 31 77 99 98 79
Type
O O O O O O O O O O O O O O O O O O O I/O O O I/O I/O I
Signal Name
PCM_WE_L PCM_WP PCTL[0] PCTL[1] PCTL[2] PDREQ_L PIRQ_L[0] PIRQ_L[1] PRDY PSLEEP_L PTYPE RESET_L V3V_CORE V3V_CORE V3V_O V3V_O V5V_O V5V_O VDD_HI VSS_CORE VSS_CORE VSS_O VSS_O VSS_O VSS_O
Pin No.
58 92 97 96 95 27 2 3 28 100 29 1 12 63 22 9 46 72 70 15 65 20 41 7 74
Type
O I O O O O O O O I I I - - - - - - - - - - - - -
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PIN INFORMATION
PRELIMINARY DATA BOOK v1.0
November 1997
CL-PS6700
Low-Power PC Card Controller
Table 1-2.
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Numerical Listing
Type
I O O I/O I/O I/O - I/O - I/O I/O - I/O I/O - I I/O I/O I/O - I/O - I/O I/O I/O
Signal Name
RESET_L PIRQ_L[0] PIRQ_L[1] MD[0] MD[1] MD[2] VSS_O MD[3] V3V_O MD[4] MD[5] V3V_CORE MD[6] MD[7] VSS_CORE PCLK MD[8] MD[9] MD[10] VSS_O MD[11] V3V_O MD[12] MD[13] MD[14]
Pin No.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Signal Name
MD[15] PDREQ_L PRDY PTYPE PCE_L PCM_REG_L PCM_D[3] PCM_D[4] PCM_D[11] PCM_D[5] PCM_D[12] PCM_D[6] PCM_D[13] PCM_D[7] PCM_D[14] VSS_O PCM_CE[1] PCM_D[15] PCM_A[10] PCM_CE[2] V5V_O PCM_OE_L PCM_A[11] PCM_IORD_L PCM_A[9]
Type
I/O O O I I O O O O O O O O O O - O O O O - O O O O
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Signal Name
PCM_IOWR_L PCM_A[8] PCM_A[17] PCM_A[13] PCM_A[18] PCM_A[14] PCM_A[19] PCM_WE_L PCM_A[20] PCM_RDY PCM_A[21] PCM_A[16] V3V_CORE PCM_A[22] VSS_CORE PCM_A[15] PCM_A[23] PCM_A[12] PCM_A[24] VDD_HI PCM_A[25] V5V_O PCM_A[7] VSS_O PCM_A[6]
Type
O O O O O O O O O I/O O O - O - O O O O - O - O - O
Pin No.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
Signal Name
PCM_A[5] PCM_RESET PCM_A[4] PCM_WAIT PCM_A[3] PCM_A[2] PCM_A[1] PCM_BVD[2] PCM_A[0] PCM_BVD[1] PCM_D[0] PCM_D[8] PCM_D[1] PCM_D[9] PCM_D[2] PCM_D[10] PCM_WP PCM_CD[2] PCM_CD[1] PCTL[2] PCTL[1] PCTL[0] PCM_VS[2] PCM_VS[1]
Type
O O O I O O O I O I O O O O O O I I I O O O I/O I/O I
100 PSLEEP_L
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PIN INFORMATION
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CL-PS6700
Low-Power PC Card Controller
2. PIN DESCRIPTIONS
2.1 CL-PS7111-to-CL-PS6700 Interface Signals
The conventions used for the power sources on the CL-PS7111-to-CL-PS6700 interface are listed in Table 2-1. Table 2-1.
Symbol
sys pcm VDDhi
a
Power Source Conventions a
Power Source
system PCMCIA VDDhi pin
See Section 2.3 on page 17 for details on power and ground pins.
2.1.1 Address/Data Bus Signals
Signal
MD[15:0]
Type
I/O
Power Description Source
sys Multiplexed address and data bus: The MD bus carries address information during a two-clock address phase and data during a one- or two-clock data phase. Address Phase: A PC Card address is a 26-bit byte address. The MD bus carries the upper 10 address bits, plus control bits during the first clock of Chip Enable (PCE_L low), and the remaining (lower) 16 address bits during the second clock.
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PIN DESCRIPTIONS
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CL-PS6700
Low-Power PC Card Controller
2.1.1 Address/Data Bus Signals (cont.)
Signal Type Power Description Source
sys Data Phase: If a write transfer is indicated (during the address phase), write data appears in the third clock (also a word write, during the fourth clock) of Chip Enable. For register read transfers, a two-clock data phase follows the two clocks of address phase after a one clock bus turnaround cycle. For card reads, the data phase is deferred until card data has been collected as signaled by PRDY; the data phase is initiated by a second assertion of PCE_L, and the CL-PS6700 drives this bus with read data in the clock following the assertion of PCE_L (if a word read, during the second clock following PCE_L). The data phase of MD[15:0] carries the transfer size and space required for the data (see Table 2-2 and Table 2-3). SLOT[1:0] is a space reserved for future expansion.
MD[15]
SIZE[1:0] SLOT[1:0] SPACE[1:0] A[25:16]
MD[15:0] I/O (cont.)
MD[0]
1st Clock of Address Phase MD[15]
A[15:0]
MD[0]
2nd Clock of Address Phase
Table 2-2.
Transfer Size
Table 2-3. Area Accessed
SIZE[1:0]
00 11
Number of bytes
1 4
SPACE[1:0]
00 01 10 11
Area Accessed
Attribute space I/O space Common memory CL-PS6700 register space
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PIN DESCRIPTIONS
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CL-PS6700
Low-Power PC Card Controller
2.1.2 Access Control Signals
Signal
PCE_L
Type
I
Power Description Source
sys PC Card Chip Enable: This signal, if asserted, enables the strobing of address and data information between the CL-PS7111 and the CL-PS6700 through the MD bus. For a read from PC Card memory or I/O space, the CL-PS7111 asserts PCE_L during the address phase and (possibly much later) during the data phase of a read transaction. Depending on the transaction, PCE_L is low for between two and five PCLK periods. When a read is pending, the CL-PS7111 waits for PRDY from the CL-PS6700 to complete the data phase. If the CL-PS6700 does not respond within a given time period, the CL-PS7111 times out and performs a dummy data phase by asserting PCE_L without receiving PRDY, causing the CL-PS6700 to abort the card read. If the CL-PS6700 times out card writes, it issues a WR_FAIL interrupt. PC Card Transaction Type: During the first clock of PCE_L, this signal indicates whether the operation is a write or a read. A low level indicates a write and a high level indicates a read. During the second clock of the address phase, this signal indicates if the transaction was initiated by the CPU or an optional DMA controller. A low level indicates the DMA controller, and a high level indicates the CPU. If initiated by the DMA controller and the address targets the card's I/O space, a properly configured CL-PS6700 performs a DMA transfer at the card. This feature is not supported by the CL-PS7111 and is for future use only.
PTYPE
I
sys
Table 2-4.
PTYPE Signal Encoding During PCE_L
MD Bus Transfer Type
PTYPE during Address Phase Cycle 1 (RD/WR) Cycle 2 (CPU/DMA)
0 0 1 1 0 1 0 1 Write operation initiated by DMA controller. Write operation initiated by CPU. Read operation initiated by DMA controller. Read operation initiated by CPU.
PRDY
I/O
sys
NOTE: PRDY should be pulled up with a 100-k resistor. PC Card ready: This signal goes to the CL-PS7111 and serves as both an address ready and data ready signal. It can also indicate a busy (card RDY/BUSY pin) status of the corresponding PC Card socket (see configuration bit "Include Card Ready in PRDY"). Normally, the CL-PS6700 leaves this signal asserted (high). When the CL-PS7111 targets a read or write transaction to the CL-PS6700, the CL-PS6700 deasserts PRDY in the second clock of the address phase until it has processed the transaction. For a card write, PRDY remains deasserted only if the write queue becomes full due to the current transaction. Otherwise, PRDY is reasserted during the next clock. When the CL-PS6700 write queue is full, PRDY is reasserted only after a queued write is disassembled (if necessary) and propagated to the PC Card socket, freeing an entry in the write queue. Therefore, the CL-PS7111 is assured that it does not get data wait states for card write operations. For a card read, the CL-PS6700 asserts PRDY when it has collected the required bytes from the PC Card. The CL-PS7111 then initiates the data phase by issuing a second PCE_L without driving the MD bus to the CL-PS6700(s). Then, the CL-PS6700 with a posted read responds with the read data. The CL-PS6700 registers can be read regardless of the state of PRDY. Therefore, PRDY cannot toggle during the address phase of register access if it is already deasserted. PRDY is a don't care input to the CL-PS7111 during the four (for write) or five (for read) clocks of register accesses.
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PIN DESCRIPTIONS
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CL-PS6700
Low-Power PC Card Controller
2.1.2 Access Control Signals (cont.)
Signal Type Power Description Source
sys PC Card DMA Request: When configured as PDREQ_L, this wire-OR'ed signal indicates to the CL-PS7111 that one of the PC Card sockets has issued a DMA request. Since this is shared by all PC Card sockets, the system should enable DMA to only one socket at a time and program the CL-PS7111 DMA routine. General-Purpose I/O: When configured as GPIO, this signal can be used as an input capable of generating an interrupt. As a general-purpose output, it is actively driven in both output states, high and low.
PDREQ_L/ I/O GPIO
2.1.3 Interrupt and Abort Signals
Signal Type Power Description Source
sys PC Card Interrupt Request: The interrupt request lines can be wire-OR'ed if there are two CL-PS6700 controllers. It signals that one or two CL-PS6700s have an interrupt pending. The exact source of pending interrupts can be read in a CL-PS6700 Interrupt Source register. External pull-up resistors for these signals are required. Alternatively, every interrupt request line can be connected to one of the CL-PS7111 active-low interrupt inputs.
PIRQ_L[1:0] OD-O
2.1.4 Clock, Reset, and Sleep Signals
Signal
PCLK
Type
I
Power Description Source
sys All transfers between the CL-PS7111 and the CL-PS6700 are synchronous to this clock signal. To conserve power, PCLK can be disabled when the PC Card subsystem is not in use. This reset signal can be driven by one of the GPIO outputs of the CL-PS7111 or by a system reset. It is an active-low input and places all CL-PS6700 registers and outputs in their default power-up/reset condition. The CL-PS7111 drives this signal either by the RUN output or by any GPIO. This active-low signal is synchronous to the rising edge of PCLK. PSLEEP_L causes the CL-PS6700 to complete or abort (as configured) any card operation in progress, enter the lowest power mode, and disable its I/O according to the Table 4-2 on page 32. The CL-PS7111 can discontinue transactions to CL-PS6700 before asserting PSLEEP_L; if a card transaction in progress or in the queue is lost due to PSLEEP_L being asserted, an interrupt (RD_FAIL or WR_FAIL) is generated. There must be two PCLKs after PSLEEP_L is asserted to go into Standby mode.
RESET_L
I
sys
PSLEEP_L
I
sys
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CL-PS6700
Low-Power PC Card Controller
2.2 PC Card Interface Signals
A PC Card socket can be configured as either memory only or combined I/O-memory. Some pins on the PC Card interface have different meanings in memory and I/O modes. These pins are listed as dual-mode. The mode is selected by a configuration register bit. When I/O mode is programmed, the CPU accesses either I/O space or memory space on the card according to the upper address bits. The CPU Attribute memory is accessible in either memory or I/O modes, again, selected by the upper address bits. A card DMA device is accessible only in I/O mode.
2.2.1 Address and Data Signals
Signal
PCM_D[15:0]
Type
I/O
Power Description Source
pcm PC Card data bus: Single-mode. Data transfer can be either byte or half-word (16-bit) as configured by the CPU. All byte accesses are transferred through their natural byte lane only (odd bytes on PCM_D[15:8] and even bytes on PCM_D[7:0]). PC Card address bus: Single-mode. This is a byte address during byte operations and a halfword address during half-word (16-bit) accesses (that is, A[0] is kept low).
PCM_A[25:0]
O
pcm
2.2.2 Access Control Signals
Signal
PCM_CE_L[2:1]
Type
O
Power Description Source
pcm Card enables: Single-mode. These are the byte enable lines for the data bus. PCM_CE_L[1] enables even bytes, D[7:0], and PCM_CE_L[2] enables odd bytes, D[15:8]. Output enable for memory read data. Single-mode. PCM_OE_L enables the card's data outputs. During a write operation, this signal is deasserted (high). During a card read DMA transfer, this signal is used as a terminal count and is asserted along with PCM_IORD_L during the last DMA card read. Write enable signal for common memory and DMA: Single-mode. During a card write DMA transfer, this signal is used as a terminal count and is asser ted along with PCM_IOWR_L during the last DMA card write.
PCM_OE_L
O
pcm
PCM_WE_L
O
pcm
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CL-PS6700
Low-Power PC Card Controller
2.2.2 Access Control Signals (cont.)
Signal
PCM_REG_L
Type
O
Power Description Source
pcm Single-mode. This signal, in conjunction with the card data strobes, PCM_OE_L, PCM_WE_L, PCM_IORD_L, and PCM_IOWR_L, determine which of the three address spaces (I/O, common memory, or attribute memory) is chosen and if the transfer is a DMA or non-DMA type. 1 - common memory or DMA access 0 - I/O space or attribute memory space access Table 2-5. PC Card Access Types
Card Access Type
Common Memory Read/Write Attribute Memory Read/Write Card I/O Read/Write Card DMA Read/Write
PCM_OE_L PCM_WE_L
Data strobe Data strobe Deasserted Terminal count
PCM_IORD_L PCM_REG_L PCM_IOWR_L
Deasserted Deasserted Data strobe Data strobe Deasserted Asserted Asserted Deasserted
PCM_WP
I
pcm
Dual-mode. Memory Mode: This signal indicates that the card has been set to be write-protected. I/O Mode: This signal becomes IOIS16_L. An asserted level (low) indicates that the I/O card is a 16-bit device. If IOIS16_L is not asserted (high), the device is assumed to be 8-bit, and data transfer occurs over byte lane D[7:0]. In this mode, the WP status of the card is available as an on-card register bit. DMA Mode: This signal can be selected as DREQ from the PC Card.
PCM_WAIT_L
I
pcm
Single-mode. This data wait signal is used by the card to delay completion of an in-progress memory or I/O access cycle. It is sampled by the CL-PS6700 with a flip-flop clocked on the rising edge of PCLK, then fed to the card interface logic. In order to be recognized, this signal must be asserted at least two clocks before the end of the command strobe. Dual-mode. Memory Mode: This signal is deasserted while the card is busy processing a previous transfer. It is intended to signal the completion of potentially lengthy operations within the card. This signal is available as a status bit for polling by the CPU, and can generate an interrupt to the CPU. It can also form the PRDY signal to the CL-PS7111 for handshake, preventing masters from targeting a busy card. I/O Mode: This signal is IREQ_L, an interrupt request generated by the I/O card. The RDY function of memory mode is available as an on-card register bit. DMA Mode: This input can be selected as DREQ from the PC Card.
PCM_RDY
I
pcm
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Low-Power PC Card Controller
2.2.3 Additional Control for I/O Signals
Signal
PCM_IORD_L PCM_IOWR_L
Type
O
Power Description Source
pcm Single-mode. Dual-mode. Memory Mode: These signals remain deasserted. I/O Mode: These signals are asserted during read (PCM_IORD_L) and write transfer (PCM_IOWR_L) to the card I/O space or DMA devices. A PC Card does not respond to these signals unless it is configured for I/O by the system.
2.2.4 Card Detect and Battery Status Signals
Signal
PCM_CD_L[2:1]
Type
I
Power Description Source
VDDhi 00 - Card inserted 01 - Card partially inserted 10 - Card partially inserted 11 - Card not inserted Single-mode. These pins indicate whether a card has been inserted into a socket. They are positioned at opposite ends of the connector to ensure valid detection of card insertion; a properly inserted card pulls both lines low. They are pulled up to VDDhi within the CL-PS6700 until a card is inserted (which pulls them low). These signals are available as status bits in a register, and any state change can also cause an interrupt informing the system that a card has been inserted or removed.
PCM_BVD[2:1]
I
pcm
Dual-mode. Memory Mode: These bits indicate the card battery condition as outlined in Table 2-6. Table 2-6. PC Card Battery Voltage Detect Encoding
PCM_BVD[2:1]
X0 01 11
Battery Condition
Battery dead Battery low Battery OK
I/O Mode: PCM_BVD[2] becomes SPKR_L, the Audio Digital Waveform signal, while PCM_BVD[1] becomes the STSCHG_L signal, a status line that indicates state changes of BVD, CD, and WP. The state of the BVD inputs can be read by the CPU in the CL-PS6700 Status registers and are also available on the PC Card registers.
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CL-PS6700
Low-Power PC Card Controller
2.2.5 Card Voltages and Reset Signals
Signal
PCM_VS[2:1]
Type
I/O
Power Description Source
VDDhi Single-mode. These signals inform the host system of the voltage requirements and capabilities of the card for reading its CIS before applying power to the card. This allows 3.3-V only cards (which need not support 5-V operation during configuration). VS[2] primarily differentiates between 3.3- and 5-V cards, while VS[1] primarily differentiates between 3.3-V and X.X-V cards. These signals, and the three power control signals, are bidirectional signals under software control (register bits) for flexibility. All five signals are capable of generating interrupts. VS[2] can also be configured to act as the card DREQ input.
PCTL[2:0]
I/O
VDDhi Single-mode. These GPIO signals typically control the corresponding card's power module or switch. They determine the proper voltage for the VCC and/or the VPP pins of the socket. These signals are directly controlled by register bits and thus, can control serially-controlled power modules. They can also be programmed to transition to a new value automatically when the PSLEEP_L input is asserted to automatically shut down card power in case of power fault conditions. PCTL[2:0] are inputs during reset and therefore require an external pull-down or pull-up resistor to avoid power being applied to the card socket. pcm Single-mode. This signal resets the PC Card, placing it into its default memory-only mode. The signal remains in a high-impedance state after power-on or system reset. Cards that implement the reset function pull up this signal with >100 k. The CPU (after >1 ms) should pull this signal low by writing a `0' to bit 12 of the Card Interface Configuration register.
PCM_RESET
O
2.3 Power and Ground Pins
Signal
V3V_Core V3V_O V5V_O VDD_HI VSS_Core VSS_O
Group
core sys pcm VDDhi
Description
Power to core logic; either 5 V or 3.3 V. Power to system interface I/O buffers; either 5 V or 3.3 V, but must be the same as the CL-PS7111 power plane (V3V_Core). Power to PC Card interface I/O buffers; either 5 V, 3.3 V, or 0 V. This pin should be tied to the highest voltage in the system (as seen by CL-PS6700; either 5 V or 3.3 V). Ground pins for the core and input buffers. Ground pins for output buffers.
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CL-PS6700
Low-Power PC Card Controller
3. FUNCTIONAL DESCRIPTION
The CL-PS7111 communicates with the CL-PS6700 through the memory bus. This bus has a special multiplexed mode that uses 16 bits of the data bus to transfer address and data messages to the CL-PS6700. This split transaction bus supports posting a (single) read transaction so that the potentially long access time of a PC Card does not disrupt the memory bus. The protocol defines two clocks to transmit address messages, and one or two clocks for data messages. This allows efficient transfer of 32-bit words, as well as bytes and half words.
3.1 PC Card (PCMCIA) Interface
3.1.1 PC Card Types The supported PC Card v2.01 card types are:
q q q q
Memory-only card, such as flash or SRAM I/O card, such as a modem card Multifunction cards with both I/O and memory DMA-capable cards
Each card can be 3.3 V or 5 V, and power to each card is managed independently by the CL-PS7111 and the corresponding CL-PS6700. General-purpose digital I/O (PCM_VS pins on the CL-PS6700) can be used by the CPU to detect the voltage requirements of a card before applying power. 3.1.2 PC Card Address/Data Bus The PC Card supports a 26-bit address bus and a 16-bit data bus. The CL-PS7111 multiplexes these buses into a single 16-bit bus MD[15:0]. This bus is demultiplexed by the CL-PS6700, which also implements the low-level interface to the PC Card and provides voltage translation for mixed-voltage systems. The CL-PS6700 also provides data buffering, endian conversion, and interrupt control for the PC Card. Transfers between the CL-PS7111 and the CL-PS6700 are one or four bytes. The CL-PS7111 accesses the CL-PS6700 as a memory-mapped peripheral on the memory bus. A chip enable signal, PCE_L of CL-PS6700, is connected to CS[4] (and CS[5] for a second PC Card socket) from the CL-PS7111. 3.1.3 PC Card Address Spaces and DMA The PC Card standard defines three address spaces for PC Cards: memory space, I/O space, and attribute space. Each of these is 64 Mbytes, requiring 26 address bits, while other command bits select the space to be accessed. Attribute memory space contains setup information such as the CIS. Attribute memory is accessed as an 8-bit device, but only at half-word boundaries (even bytes only). Memory and I/O space for a card can each be 8 or 16 bits in width. The width of the access made to each of these spaces by the CL-PS6700 is software configurable. In addition, I/O space accesses can be sized dynamically by the PCM_WP (IOIS16_L) input. All three address spaces for each card are mapped into the CL-PS7111 memory map and are directly accessible by the CPU. In addition to these three address spaces, a card can contain a DMA target. The
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CL-PS6700
Low-Power PC Card Controller
CL-PS7111 does not implement a DMA controller for the PC Card, but the CPU can emulate DMA cycles by appropriately configuring the CL-PS6700, then accessing card I/O space (see Table 4.4.2 on page 27). In this case, the CL-PS6700 accesses the card using a newly defined DMA cycle (IORD/WR strobes used with -REG high). The PC Card standard requires all cards to follow the little-endian memory model. The CL-PS7111 can support both the little-endian and big-endian modes of operation. Thus, the CL-PS6700 provides for endian conversion, which is software configurable. 3.1.4 Byte Assembly/Disassembly and Queueing Since all spaces on the cards (even I/O cards) are memory mapped, the CL-PS7111 can access the cards directly. The CL-PS6700 can be programmed to assemble/disassemble the CL-PS7111 transfers to the width of the PC Card. The CL-PS6700 has read and write buffers, allowing posting of both reads and writes. The read queue is single entry, and the write FIFO can queue up to four CL-PS7111 transactions (up to 16 bytes). Reads do not bypass queued writes (card transactions are processed in order). Certain card access timing parameters are programmable and can be set to operate faster than the PC Card specification allows. The CL-PS6700 contains a watchdog timer that ensures that a card access is aborted if it exceeds a preprogrammed time limit, generating an interrupt to the CL-PS7111. 3.1.5 Card Configuration After power-on or reset, a PC Card defaults to a memory-only card. The CPU then reads the card's CIS to determine the card type, access time, and so on, configuring the CL-PS6700 to properly access the card. Each PC Card's VCC and VPP pins are individually controlled by its corresponding CL-PS6700 pins. The CL-PS7111 controls the power to a card by writing to the CL-PS6700 registers. The CL-PS6700 ensures that its signals to the sockets are in the proper state before applying and removing power to the sockets. 3.1.6 Hot Insertion Support PC Cards are often used like floppies: The user can insert or remove cards while system power is on. Typically, the CPU only applies power to a PC Card socket after it has detected a properly inserted card and removes the power before the card is removed (that is, when the CPU detects that card lock is deasserted). Since each card is isolated from the system by its CL-PS6700, insertion and removal of cards should not cause glitches on the system buses.
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CL-PS6700
Low-Power PC Card Controller
3.2 Power States
3.2.1 Active State The Active State is the normal operating state entered whenever PC Card accesses are required. In this state the PCLK input is active, the PSLEEP_L input is deasserted, and the Idle bit in the Power Management register is cleared. 3.2.2 Idle State Normally, Idle State is entered/exited dynamically in hardware (by CL-PS6700 control logic) transparent to software. This method is invoked by setting the Enable Auto Idle Mode bit in the Power Management register, and appears identical to the Active State, except that some internal clocks are gated off between transactions to conserve power. The software can enter Idle State explicitly by setting the Idle mode. In this case, access to the CL-PS6700 registers is supported, but PC Card accesses do not propagate to the card and a read fail or write fail event can occur, which can generate an interrupt to the host. 3.2.3 Standby State Standby State is the lowest power state in the system and is entered by asserting the PSLEEP_L input. At least two (rising) clock edges are required after PSLEEP_L is asserted before the PCLK is shut off. In the Standby State the CL-PS6700 core and system interface power can remain on, but consumes near zero power (microwatts). If card transactions are queued in the CL-PS6700 when PSLEEP_L is asserted, they are either aborted or continue until finished (requiring more than two clocks), depending on the setting of bit 9 (Standby Request During Card Access) in the Power Management register.
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CL-PS6700
Low-Power PC Card Controller
4. REGISTERS
The CL-PS6700 registers are spaced at 1-Kbyte boundaries and must be accessed by the CPU in word mode (not byte mode), even though they are all 16 bits or less in actual width. The upper 16 bits of register reads should be treated as undefined. The CL-PS6700 registers are accessible in all power states where the CL-PS6700 is powered and has a running PCLK (regardless of the state of PRDY). PC Card access should be done only when the CL-PS6700 is in Active mode. Since register access circumvents the CL-PS6700 write queue, control of register bits, which can affect posted writes or prefetch reads such as applying and removing card power, should be done only after checking that the CL-PS6700 is idle using the Idle bit in the Interrupt Input Level register.
4.1 Register Addresses
The following address conventions are used in the register tables. The tables show the offset from the base addresses. In a CL-PS7111 based system, the CL-PS6700 address spaces start with base addresses 0x4000_0000 for the first PC Card socket (that is, the one connected to NCS[4]), and 0x5000_0000 for the second CL-PS6700 (connected to NCS[5]). To calculate the address for any register, add the offset (for example, 0X0C00_2800 for the Power Management register) to the base (for example, 0x4000_0000 for the CL-PS6700 connected to NCS[4]) to get the address (0X4C00_2800).
Offset from Base Address
Description
Default
R/W
0X0C002800 Power Management register 0X0C002C00 Card Power Control register 0X0C002000 System Interface Configuration register 0X0C004000 DMA Control register 0X0C004400 Device Information register 0X0C002400 Card Interface Configuration register 0X0C003000 Card Interface Timing register 0A 0X0C003400 Card Interface Timing register 0B 0X0C003800 Card Interface Timing register 1A 0X0C003C00 Card Interface Timing register 1B 0X0C000000 PC Card Interrupt Status register 0X0C000400 PC Card Interrupt Mask register 0X0C000800 PC Card Interrupt Clear register 0X0C000C00 PC Card Interrupt Output Select register
0 0 0x1F8 0 0x0040 0 0x1F00 0 0x1F00 0 0 0 XX 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W W W
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CL-PS6700
Low-Power PC Card Controller
Offset from Base Address
Description
Default
R/W
0X0C001000 PC Card Interrupt Reserved register 1 0X0C001400 PC Card Interrupt Reserved register 2 0X0C001800 PC Card Interrupt Reserved register 3 0X0C001C00 PC Card Interrupt Input Level register
0 0 0 Input Level
W W W R
NOTE: The three Reserved Interrupt registers must be written with all ones (32'hFFFFFFFF) before interrupts can be captured and output to the PIRQ[1:0] pins.
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CL-PS6700
Low-Power PC Card Controller
4.2 Interrupt Structure
Interrupt sources in the CL-PS6700 include card inputs, GPIO pins (PCTL/PDREQ_L), and internal status signals. All interrupts in the CL-PS6700 are edge triggered. There are five register bits that control each interrupt, as shwon in Table 4-1. The Interrupt Status register indicates which interrupt inputs have transitioned (rising edge or falling edge) since they were last cleared (using the Interrupt Clear register). The OR'ing of bits in the Interrupt Status register (bits not masked by the Mask register) generates an interrupt on either the PIRQ[0]_L or PIRQ[1]_L output as selected in the Interrupt Output Select register. A bit set to `1' in the Interrupt Output Select register routes the corresponding interrupt to PIRQ[1]. The Interrupt Input Level register reflects the current state of the raw interrupt sources (signals directly from the PC Card socket, GPIO pins, and internal status signals). Table 4-1. Interrupt Register Set a
Interrupt Sources Bit Position 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0
PCM_RDY_L
RESERVED
PCM_BVD2
Register Name
R/W
Interrupt Status Interrupt Mask Interrupt Clear Interrupt Output Select Interrupt Input Level
a
R R/W W R/W R
- - - - -
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x means available. - means unavailable.
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PCM_BVD1
FIFO THLD
PCTL [2:0]
PCM_CD2
PCM_CD1
PDREQ_L
PCM_VS2
PCM_VS1
PCM_WP
WR_FAIL
RD_FAIL
IDLE
x x x x x
23
CL-PS6700
Low-Power PC Card Controller
4.3 Power Management Registers
4.3.1 Power Management Register (0X0C002800)
Bit(s)
15:14 13 12
Description
Reserved Disable Protection for PCM_BVD[1] Input During Card Power Off. The input pull-up is controlled in the same way as other card inputs. Input Pull-Up Enable. This bit applies to card inputs BVD[2], BVD[1], RDY, WAIT, WP. During CardOut or Standby, the pull-up resistors are disconnected and inputs are protected regardless of the state of this bit. `Protected input' (PI) means the input can float without causing excessive current. CardOut means that the Card Detect inputs are high (no card inserted) or that the card power is off (Card Power Enable bit 5 is low and Monitor Card Power Enable bit 6 is high).
Default R/W
00 0 0 R/W R/W R/W
11:10
Card Detect. Weak internal pull-up resistor. 00 - Pull-up is off and Card Detect inputs are not protected. This assumes that there are external pull-up resistors. 01 - Pull-up is off and Card Detect inputs are protected. 10 - Weak pull-up, except when in Standby mode. 11 - Weak pull-up always on. This allows Card Detect during Standby.
00
R/W
9
Standby Request During Card Access. This bit controls pending card accesses when entering Standby mode. 0 - Abort any card access when entering Standby mode. 1 - Complete pending card access, then halt.
0
R/W
8 7 6
Standby Disable. When this bit is set, the PSLEEP_L input is effectively disabled. PDREQ_L Select. If this bit is set, the PDREQ_L pin is a GPIO pin. Monitor Card Power Enable (Bit 5). 0 - Card power is assumed to be always on. 1 - Enable monitoring of power. This bit has no effect on card power or the CL-PS6700 power modes such as Standby and Idle.
0 0 0
R/W R/W R/W
5
Card Power Enable. 0 - Outputs state of bits [5:3] of Card Power Control register to the PCTL[2:0] pins. 1 - Outputs state of bits [2:0] of Card Power Control register to the PCTL[2:0] pins. If card access is attempted with this bit clear, a RD_FAIL or WR_FAIL interrupt can be generated.
0
R/W
4 3 2 1
Auto Disable Card Access on Card Removal. If this bit is set, the Card Enable bit (bit 10 in the Card Interface Configuration register) is cleared when the card is removed. Auto Power Down Card on Card Removal. If this bit is set, the Card Power Enable bit (bit 5) is cleared when the card is removed. Auto Power Down Card on Standby. If this bit is set, the Card Power Enable bit (bit 5) is cleared when Standby mode is entered. Idle. When this bit is set, it forces the CL-PS6700 into Low Power mode. Most internal clocks are stopped with the exception of register access. Idle mode has no affect on I/O pads or card power control. Enable Auto Idle Mode. When this bit is set, some internal clocks are stopped whenever the CL-PS6700 is idle.
0 0 0 0
R/W R/W R/W R/W
0
0
R/W
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CL-PS6700
Low-Power PC Card Controller
4.3.2 Card Power Control Register (0X0C002C00)
Bit(s)
15:14
Description
VS[2:1] Direction. 0 - Input 1 - Output Input pull-up resistors are weak. During Standby mode the pull-up resistors are disabled.
Default R/W
00 R/W
13:12 11
VS[2:1] Output Value. GPIO Direction. See Note. 0 - Input 1 - Output
00 0
R/W R/W
10 9 8:6
GPIO Output Value When Card Power Enable Bit is Low. See Note. GPIO Output Value When Card Power Enable Bit is High. See Note. PCTL[2:0] Direction. 0 - Input 1 - Output
0 0 00
R/W R/W R/W
5:3
PCTL[2:0] Output Value When Card Power Enable Bit is Low. PCTL[0] is a tristate output only. PCTL[2:1] are bidirectional. The PCTL[2:1] input value is at the Interrupt Pins register and can generate an interrupt while PCTL[0] cannot generate an interrupt. PCTL[2:0] Output Value When Card Power Enable Bit is High.
000
R/W
2:0
000
R/W
NOTE: If Power Management register bit 7 is cleared, then this bit is a don't care.
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CL-PS6700
Low-Power PC Card Controller
4.4 System Interface Registers
4.4.1 System Interface Configuration Register (0X0C002000)
Bit(s)
15:10 9 8
Description
Reserved Enable Active Pull-up on Open-Drain Interrupt Outputs PIRQ_L[1:0]. During Standby, active pull-up is disabled. Enable Assembly and Disassembly. If this bit is set, assembly and disassembly of card accesses by CPU or DMA is allowed. When this bit is cleared, the card transaction size is limited to the width of the card defined by the Card Interface Configuration register bit 7. Enable Handshake Using Card Ready Signal. When this bit is set, a low-level on PCM_RDY prevents access to the card. When this bit is cleared, RDY is ignored, but can still generate interrupts. Report Read Failure. When this bit is set, a read failure generates an RD_FAIL interrupt. Read failure can occur due to a time-out condition. Normally, this bit should be cleared so the CL-PS7111 reports read failures. Endian Conversion Enable. 0 - Disable byte swapping 1 - Enable byte swapping PC Cards are defined as little-endian, while the ARM CPU inside the CL-PS7111 can be big-endian or little-endian.
Default R/W
- 0 1 - R/W R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
Transaction Queue Enable. When this bit is set, it enables queuing one or more CL-PS7111 write operations. If this bit is cleared, then PRDY goes low after a write until the write is complete. Transaction Queue Threshold Control. 0 - FIFO THLD interrupt when two entries are free in queue. 1 - FIFO THLD interrupt when four entries are free in queue. Transaction Queue Flush. Discard data in queue. Reserved
1
R/W
3
1
R/W
2 1:0
0 00
R/W R/W
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CL-PS6700
Low-Power PC Card Controller
4.4.2 DMA Control Register (0X0C004000)
Bit(s)
15:9 8 7
Description
Reserved Enable Handshake with CL-PS7111 Using PDREQ_L. If this bit is cleared, then PDREQ_L is always deasserted. If Power Management register bit 7 is set, then this bit is a don't care. Card DMA Enable. Enables card DMA transfer. A DMA transfer is defined by REG_L deasserted and IORD_L or IOWR_L asserted. OE_L and WE_L indicate the terminal count for read and write, respectively. DMA Request Input Select. Selects input to be used for DMA handshake between the CL-PS6700 and the card. Currently, there is no dedicated card pin assigned for DMA request. 000 - Disable DMA access 001 - PCTL[2] 010 - PCM_VS[2] 011 - Reserved 101 - PCM_WP input 110 - PCM_BVD2 111 - Card always requesting DMA transfer (no handshake between CL-PS6700 and card). After each DMA transfer from CL-PS7111 to CL-PS6700, PDREQ_L is immediately reasserted.
Default R/W
- 0 0 - R/W R/W
6:4
000
R/W
3 2 1
DMA Request Polarity Select. If this bit is set, the selected DMA request input (as described above) is inverted to be active-low. Transparent DMA Request. If this bit is set, then external DMA request input is passed through to the PDREQ_L output after being synchronized to PCLK. CPU Initiated DMA. This allows the CPU to generate a card DMA transfer. If this bit is set, a CPU access to I/O space is converted to a DMA transfer. REG_L is kept high (deasserted), and IORD_L or IOWR_L is used to transfer data. CPU Initiated DMA with Terminal Count. If this bit is set, a CPU access to I/O space is converted to a DMA transfer. REG_L is kept high (deasserted). The end of DMA is indicated to the card by OE_L low (read) or WE_L low (write). IORD_L or IOWR_L are used to transfer data.
0 0 0
R/W R/W R/W
0
0
R/W
4.4.3 Device Information Register (0X0C004400)
Bit(s)
7:6 5 4:2 1:0
Description
Chip ID Dual/Single Socket. Single-socket device if low. Revision Level. This changes as new revisions become available. Reserved
Default R/W
01 0 00 00 R R R R
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CL-PS6700
Low-Power PC Card Controller
4.5 Card Interface Registers
4.5.1 Card Interface Configuration Register (0X0C002400)
Bit(s)
15:13 12
Description
Reserved Card Reset. 0 - The PCM_RESET output is deasserted (low). 1 - The PCM_RESET output is asserted (high).
Default R/W
0 0 - R/W
11 10
Card Reset Output Enable. If this bit is set, PCM_RESET is driven with the value of bit 12. If this bit is cleared, the output is tristated. Card Enable. This bit must be set for the CL-PS6700 to make a card access. If a card access is attempted by the CL-PS7111 while this bit is cleared, a read time-out or WR_FAIL interrupt occurs. Card Write Protect. If this bit is set, a card is write-protected in memory and I/O mode. The card Write Protect signal protects the card only in Memory mode. Memory or I/O Mode Select. 0 - Card in memory mode. 1 - Card in I/O mode. Write Protect becomes IOIS16. Other Dual mode inputs are not interpreted by the CL-PS6700, and remain register bits that can generate interrupts. CAUTION: This bit must be set when interfacing to the CL-PS7111 when addressing I/O space; otherwise the system may hang.
0 0
R/W R/W
9 8
0 0
R/W R/W
7 6
Card Access Width. If this bit is set, the card width for memory and I/O access is 16 bits. If the Auto Size bit is set, then I/O access width is determined by IOIS16_L rather than this bit. Auto Size I/O Accesses. 0 - I/O access width on the PC Card bus is determined by the Card Access Width bit. 1 - Dynamic bus sizing is enabled. If IOIS16_L is asserted, the data width is 16 bits; otherwise, it is 8 bits.
0 0
R/W R/W
5
Timer Select for Memory Space Write. 0 - Select timer 0 (0A and 0B) 1 - Select timer 1 (1A and 1B)
0
R/W
4
Timer Select for Memory Space Read. 0 - Select timer 0 1 - Select timer 1
0
R/W
3
Timer Select for I/O Space Write. 0 - Select timer 0 1 - Select timer 1
0
R/W
2
Timer Select for I/O Space Read. 0 - Select timer 0 1 - Select timer 1
0
R/W
1
Timer Select for Attribute Space Write. 0 - Select timer 0 1 - Select timer 1
0
R/W
0
Timer Select for Attribute Space Read. 0 - Select timer 0 1 - Select timer 1
0
R/W
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CL-PS6700
Low-Power PC Card Controller
4.5.2 Card Interface Timing Register 0A (0X0C003000)
Bit(s)
15:14
Description
Prescaler Field for Watchdog Timer. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
Default R/W
00 R/W
13:8
Count Field for Watchdog Timer. Settings of 00 to 3Fh correspond to values between 1 and 64 times the prescale value. The period starts at the end of the command width period and continues as long as PCM_WAIT_L is low. If terminal count is reached, an interrupt can be generated. Prescaler Field for Command Strobe Width. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
1Fh
R/W
7:6
00
R/W
5:0
Count Field for Command Strobe Width. This field has values between 1 and 64. The command width equals: tCMD = tPCLK x ([Prescale x Count] + 2)
00h
R/W
4.5.3 Card Interface Timing Register 0B (0X0C003400)
Bit(s)
15:14
Description
Prescaler Field for Address and Data Hold Time. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
Default R/W
00 R/W
13:8
Count Field for Hold Period. Settings of 00 to 3Fh correspond to 1 to 64 times the prescale value. The period starts at the end of the command strobe. The hold time equals: tHold = tPCLK x ([Prescale x Count] + 1) + constant
00h
R/W
7:6
Prescaler Field for Address and Data Setup Time. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
0
R/W
5:0
Count Field for Address and Data Setup Time. Settings of 00 to 3Fh correspond to 1 to 64 times the prescale value. The period starts at valid address and ends when the command strobe is active. The setup time equals: tsetup = tPCLK x ([Prescale x Count] + 1) - constant
0
R/W
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CL-PS6700
Low-Power PC Card Controller
4.5.4 Card Interface Timing Register 1A (0X0C003800)
Bit(s)
15:14
Description
Prescaler Field for Watchdog Timer. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
Default R/W
00 R/W
13:8
Count Field for Watchdog Timer. Settings of 00 to 3Fh correspond to values between 1 and 64 times the prescale value. The period starts at the end of the command width period and continues as long as PCM_WAIT_L is low. If terminal count is reached, an interrupt can be generated. Prescaler Field for Command Strobe Width. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
1Fh
R/W
7:6
00
R/W
5:0
Count Field for Command Strobe Width. This field has values between 1 and 64. The command width equals: tCMD = tPCLK x ([Prescale x Count] + 2)
00h
R/W
4.5.5 Card Interface Timing Register 1B (0X0C003C00)
Bit(s)
15:14
Description
Prescaler Field for Address and Data Hold Time. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
Default R/W
00 R/W
13:8
Count Field for Hold Period. Settings of 00 to 3Fh correspond to 1 to 64 times the prescale value. The period starts at the end of the command strobe. The hold time equals: tHold = tPCLK x ([Prescale x Count] + 1) + constant
00h
R/W
7:6
Prescaler Field for Address and Data Setup Time. 00 - Divide by 1 01 - Divide by 16 10 - Divide by 256 11 - Divide by 8192
00
R/W
5:0
Count Field for Address and Data Setup Time. Settings of 00 to 3Fh correspond to 1 to 64 times the prescale value. The period starts at valid address and ends when command strobe is active. The setup time equals: tSetup = tPCLK x([Prescale x Count] + 1) - constant
00h
R/W
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CL-PS6700
Low-Power PC Card Controller
4.6 I/O Properties
Table 4-2 on page 32 summarizes the CL-PS6700 signals.
Conventions for Table 4-2
Acronym Assert
H L Voltage high Voltage low
Definition
Type
O I I/O Output Input Bidirectional signal
Power Group
sys pcm VDDhi System PCMCIA VDD_HI pin
a
Synchronous Signal
S A
Synchronous signal Asynchronous signal
Resistor
PU PD Pull-up resistor Pull-down resistor
b
Reset, Standby, Card Power Off, Idle
T A PO PI N
a b
Output in high-impedance Normally operating output; can be high, low, or high-impedance. The state of an output during the deep Standby state is programmable, either low or high. Protected input; that is, the internal input buffer is de-coupled from the pin. Normally operating input
Synchronous signal indicates whether a signal is synchronous to PCLK. These indicate the state of each output signal or the input pin during various states of the device. For Reset, Table 4-2 on page 32 indicates the state of each signal when RESET_L is asserted and power stabilizes.
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CL-PS6700
Low-Power PC Card Controller
Table 4-2.
Signal
CL-PS6700 I/O Properties
Card Power Off Alternate Name Resistor Standby Assert Power Group Reset Load pF 10 10 10 10 10 25 10 50 10 50 50 70 10 10 10 10 10 50 50 50 50 50 50 50 100 50 10 50 50 10 50 10 Type Idle a N N N N N A N A N A A A N N N N N A A A A A A A A A PI N A N A N SYN S A A S S S S S S A A S S A A A A A S S S S S S S S A S S A S A
CL-PS7111 Interface: Multiplexed Address/Data Bus and Control PCLK RESET_L PSLEEP_L PCE_L PTYPE PRDY PDREQ_L PIRQ_L[0] PIRQ_L[1] MD[15:0] PC Card Interface PCM_WP PCM_BVD[2:1] PCM_RDY PCM_WAIT_L PCM_CE_L[2:1] PCM_REG_L PCM_OE_L PCM_WE_L PCM_IORD_L PCM_IOWR_L PCM_RESET PCM_A[25:0] PCM_D[15:0] PCM_CD_L[2:1] PCM_VS[2:1] PCTL[2:0]
a
H L L L H INIT H L L L H
I I I I I O I O I O O O I I I I I O O O O O O O O O I I O I O I
sys sys sys sys sys sys sys sys sys sys sys sys sys pcm pcm pcm pcm pcm pcm pcm pcm pcm pcm pcm pcm pcm pcm VDDhi VDDhi VDDhi VDDhi VDDhi
none none none none none none none none prog. PU none none none none prog. PU prog. PU prog. PU prog. PU none none none none none none none none none none prog. PU none prog. PU none prog. PU
N N N N N T N T N T T T N PI PI PI PI T T T T T T T T T PI PI T PI T N
N N N N N A N PO N A A A N N N N N A A A A A A A A A PI prog. PI A N PO N
N N N N N A N A N A A A N PI PI
b
H H H L L L L L L L L H H Prog. Prog. Prog.
PI PI T T T T T T T T T PI N T PI A N
The Idle mode is entered and exited by writing the register bit Idle. In Idle mode most internal clocks are gated off, and only the CL-PS6700 register access is supported. All CL-PS6700 inputs and outputs function normally. b The PCM_BVD[1] input protection can be disabled during Card power-off.
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CL-PS6700
Low-Power PC Card Controller
5. ELECTRICAL SPECIFICATIONS
Table 5-1. Absolute Maximum Ratings
Description
Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground Operating power dissipation Standby state power dissipation Power supply voltage Injection current (latch up)
Absolute Maximum Rating
0oC to 70oC -65oC to 150oC -0.3 to VCC + 0.5 V 100 mW 10 W 7V 25 mA
NOTE: Stressing the device above those listed in Absolute Maximum Ratings may cause permanent damage to the component. These are stress ratings only. Functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
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CL-PS6700
Low-Power PC Card Controller
Table 5-2.
DC Specifications
MIN
3.0 0.7 VCC 2 8 -1 -4 0.5 VCC - 0.5 -10 -1 -30 10 1 -300 10 10 15 3 YMMV c <20 <20 YMMVc <20 0 20 6 <35 <12 <20 <25 <6
Symbol Parameter
VCC5V VCC3V VILC VIHC IOL6 IOL12 IOH6 IOH12 VOL VOH Power supply voltage Power supply voltage Input low voltage CMOS Input high voltage CMOS Output low current - 2mA type Output low current - 8mA type Output high current - 2mA type Output high current - 8mA type Output low voltage Output high voltage Input leakage Input leakage - power down type Internal pull-up current Input capacitance Output capacitance Power supply current, Active mode - V3V_CORE Power supply current, Idle mode - V3V_CORE Power supply current, Active mode - V3V_O Power supply current, Idle mode - V3V_O Power supply current, Standby mode - V3V_O Power supply current, operating (Run) - V5V_O Power supply current, Idle mode - V5V_O Power supply current, Standby mode - V5V_O Power supply current, Active mode - V3V_CORE Power supply current, Suspend (Idle) - V3V_CORE Power supply current, suspend (Idle) - V3V_O
Typical
MAX
5.5 3.6 0.2 VCC
Unit Conditions
V V V V mA mA mA mA V V Normal operation Normal operation a Normal operation Normal operation Normal operation: VCC3V = MIN Normal operation: VCC3V = MIN Normal operation: VCC3V = MIN Normal operation: VCC3V = MIN Normal operation: at rated IOL Normal operation: at rated IOH Normal operation: 0 < VIN < VCC Pad power-down active Normal operation Normal operation Normal operation VCC3V = 3.3 V, PCLK = 18 MHz VCC3V = 3.3 V, PCLK = DC b VCC3V = 3.3 V, PCLK = 18 MHz VCC3V = 3.3 V, PCLK = DC VCC3V = Lithium backup V PCLK = DC (stopped) VCC5V = 5.0 V, PCLK = 18 MHz VCC5V = 5.0 V, PCLK = DC VCC5V = 0 V PCLK = DC VCC3V = 5.0 V, PCL = 18 MHz VCC3V = 5.0 V, PCLK = DC VCC3V = 5.0 V, PCLK = DC
IL ILPD IPU
CIN COUT ICCtot1 ICCtot2 ICCtot4 ICCtot5 ICCtot6 ICCtot7 ICCtot8 ICCtot9 ICCtot10 ICCtot11 ICCtot13
a b
A A A
pF pF mA mA mA
A A
mA
A A
mA mA
A
Can be run at 4.5 to 5.5 V for higher performance, but at a cost of increased power consumption (tbd). As low as 2.7 V. c This is system-design dependent, since it supplies power to the pads only.
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ELECTRICAL SPECIFICATIONS
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CL-PS6700
Low-Power PC Card Controller
5.1 Bus Timing -- System Bus
Table 5-3.
Symbol
t1a t1b t2a t2b t3a t3b t3c t3d t3e t3f t3g t4a t4b t4c t4d t4e t4f t4g t5a t5b t5c t6a t6b t6c t6d t6e t6f t18a t18b
System Bus Timing Parameters
Parameter
PCE_L input setup PCE_L input hold PTYPE input setup PTYPE input hold MD bus address phase input setup MD bus address phase input hold MD bus data phase input setup MD bus data phase input hold PCLK high to MD bus output new data PCE_L to MD bus output driven PCLK high to MD bus output High-Z PRDY input setup PRDY input hold RESET_L input high to PRDY input high PCLK high to PRDY low PCLK high to PRDY high PCLK high to PRDY output driven RESET_L low to PRDY output High-Z External interrupt to PIRQ_L[1:0] low PCLK high to PIRQ_L[1:0] low (internal interrupt sources) PIRQ_L[1:0] low-to-high during Wake mode PDREQ_L input setup PDREQ_L input hold PCLK to PDREQ_L high/low PCLK high to PDREQ_L driven PCLK high to PDREQ_L High-Z (when GPIO) PCLK low to PDREQ_L High-Z (when PDREQ_L) PCTL inputs setup PCTL inputs hold 6 8 6 8 31 30 30 30 6 8 1 x TPCLK 25 25 25 35 40 45 8 x TPCLK 8 30
MIN
12 6 8 8 7 12 7 12
MAX
Unit
ns ns ns ns ns ns ns
36
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CL-PS6700
Low-Power PC Card Controller
Table 5-3.
Symbol
t18c t18d t18e t18f t16c t17a t17b
System Bus Timing Parameters (cont.)
Parameter
PCLK high to PCTL outputs PCM_CD_L high to PCTL[2:0] outputs PCLK high to PCTL driven PCLK high to PCTL High-Z RESET_L input pulse width PSLEEP_L input setup PSLEEP_L input hold 2 x TPCLK 6 8 8
MIN
MAX
45 35 35 35
Unit
ns ns ns ns ns ns ns
Table 5-4.
Symbol
t7a t7b t7c t7d t7e t7f t8a t8b t8c t8d t8e t9a t9b t9c t9d t10a t10b t11 t12 t13
PC Card Bus Timing Parameters
Parameter
MD to PCM_A, PCM_REG_L, PCM_CE_L outputs PCLK low to PCM_A, PCM_REG_L, PCM_CE_L outputs PCLK high to PCM_A, PCM_REG_L, PCM_CE_L outputs PCLK high to card outputs a Driven PCLK high to card outputsa High-Z PCM_CD_L high to card outputsa High-Z PCM_D input setup PCM_D input hold PCLK low to PCM_D outputs PCLK low to PCM_D driven (following card read) PCLK high to PCM_D High-Z (card read) PCLK high to command strobes b low PCLK high to command strobesb high PCLK low to command strobesb low (DMA terminal count) PCLK low to command card inputs c setup card inputsc hold PCM_A, PCM_REG_L, PCM_CE_L to command strobeb low setup Command strobeb width strobesb high (DMA terminal count) 12 8 eqn 1 eqn 2 eqn 3 8 6 10 40 40 45 32 32 32 32 ns ns ns ns ns ns ns ns ns ns ns ns
MIN
MAX
n/a n/a 40 40 50 45
Unit
ns ns ns ns ns ns ns
Command strobeb high to PCM_A, PCM_REG_L, PCM_CE_L hold
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CL-PS6700
Low-Power PC Card Controller
Table 5-4.
Symbol
t14 t15c t15d t15e t19a t19b t19c
a b
PC Card Bus Timing Parameters (cont.)
Parameter
PCM_D to command strobeb high setup PCLK high to PCM_VS output PCLK high to PCM_VS output driven PCLK high to PCM_VS output High-Z PCLK high to PCM_RESET output PCLK high to PCM_RESET output driven PCLK high to PCM_RESET output High-Z 6 6
MIN
eqn 4
MAX
Unit
ns
35 35 35 35 35 35
ns ns ns ns ns ns
Card outputs refer to PCM_A, PCM_REG_L, PCM_CE_L, PCM_OE_L, PCM_WE_L, PCM_IORD_L, and PCM_IOWR_L. Command strobe refers to PCM_OE_L, PCM_WE_L, PCM_IORD_L, and PCM_IOWR_L. c Card inputs refer to PCM_CD_L, PCM_VS_L, PCM_BVD, PCM_WP, PCM_WAIT_L, and PCM_RDY.
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CL-PS6700
Low-Power PC Card Controller
5.2 Bus Operations
ADDR PHASE CYCLE 1
ADDR PHASE CYCLE 2
DATA PHASE CYCLE 1
DATA PHASE CYCLE 2
PCLK
PCE_L
t1a t2a t3a t2b t3b t3a t3b t3c t3d
DATA MSB
t1b
PTYPE
t3c t3d
DATA LSB
MD[15:0]
ADDR. HI
ADDR. LO
t4e
PRDY PCM_A PCM_REG_L PCM_CE_L
t4d
t7a t7b t8c
PCM_D PCM_WE_L PCM_IOWR_L
t9a
Figure 5-1. Memory or Register Write
ADDR PHASE CYCLE 1
ADDR PHASE CYCLE 2
MD BUS TURN-AROUND
DATA PHASE CYCLE 1
DATA PHASE CYCLE 2
PCLK
t1a
PCE_L
t1b
t2a
PTYPE
t2b
t3a
MD[15:0]
t3b
t3a t3b
ADDR. LO
t3a
t3a
DATA MSB
t3b
DATA LSB
ADDR. HI
t4d
PRDY
t4e
Figure 5-2. Register Read
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CL-PS6700
November 1997
ADDR PHASE CYCLE 2 DATA PHASE CYCLE 1 DATA PHASE CYCLE 2
ADDR PHASE CYCLE 1
PCLK
Low-Power PC Card Controller
t1a t1a t2a t2b
t1b
t1b
PCE_L
PRELIMINARY DATA BOOK v1.0
PTYPE
t3a t3b
Addr. Hi Addr. Lo
t3a t3b
t3f
DATA MSB
t3a
t3b
DATA LSB
MD[15:0]
t4d
t4e
PRDY
PCM_A PCM_REG_L PCM_CE_L
t7a t7b t8e t8a
DATA IN
Figure 5-3. System Bus: Card Data Read
t8b t8d t9a t9b
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PCM_D
ELECTRICAL SPECIFICATIONS
PCM_OE_L PCM_IORD_L
39
CL-PS6700
Low-Power PC Card Controller
DATA IN
t9b t9a t7c t8b t8d
DATA IN
t8a
t9b t9a
PCM_D PCM_OE_L PCM_IORD_L
t8e
PCLK
t7c
Figure 5-4. PC Card Bus Read Operation
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PCM_A PCM_REG_L PCM_CE_L
t11
t12
t13
t11
t12
t13
40
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CL-PS6700
Low-Power PC Card Controller
DATA OUT
t9b t9a t7c t8c
DATA OUT
t9b t9a
PCLK
t7c
PCM_A PCM_REG_L PCM_CE_L
t8c
PCM_D
Figure 5-5. PC Card Bus Write Operation
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PCM_WE_L PCM_IOWR_L
t11
t12
t13
t11
t12
t13
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CL-PS6700
Low-Power PC Card Controller
PCLK PCM_A PCM_REG_L PCM_CE_L
PCM_D
DATA OUT
PCM_IORD_L PCM_IOWR_L
t11
PCM_OE_L PCM_WE_L
t9c
t12
t9d
t13
t14
Figure 5-6. PC Card Bus DMA Transaction with Terminal Count
PCLK PSLEEP_L
t17a t17b
Figure 5-7. Standby Mode Timing
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CL-PS6700
Low-Power PC Card Controller
6. PACKAGE SPECIFICATIONS
15.56 (0.613) 16.50 (0.650) 13.90 (0.547) 14.10 (0.555) 0.08 (0.003) 0.28 (0.011)
13.90 (0.547) 14.10 (0.555)
15.56 (0.613) 16.50 (0.650) 0.50 (0.0197) BSC
CL-PS6700
100-Pin VQFP
Pin 1 Indicator
Pin 100 Pin 1
0.30 (0.012) 0.70 (0.028)
1.25 (0.049) 1.50 (0.059)
1.00 (0.039) REF
0.08 (0.003) 0.23 (0.009) 1.40 (0.055) 1.65 (0.065) 0.05 (0.002) 0.15 (0.006)
0 MIN 7 MAX
NOTES: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
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CL-PS6700
Low-Power PC Card Controller
7. ORDERING INFORMATION
CL - PS6700 - VC - A
Cirrus Logic Inc.
Personal Systems Part number Revision Temperature range: C = Commercial Package type: V = VQFP (very-tight-pitch plastic quad flat pack)
Contact Cirrus Logic for up-to-date information on revisions.
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CL-PS6700
Low-Power PC Card Controller
BIT INDEX
A
Auto Disable Card Access on Card Removal 24 Auto Power Down Card on Card Removal 24 on Standby 24 Auto Size I/O Accesses 28
M
Memory or I/O Mode Select 28 Monitor Card Power Enable 24
P
PCTL[2:0] Direction 25 PCTL[2:0] Output Value When Card Power Enable Bit is High 25 Enable Bit is Low 25 PDREQ_L Select 24 Prescaler Field for Address and Data Hold Time 29, 30 Setup Time 29 Prescaler Field for Address and Data Setup Time 30 Prescaler Field for Command Strobe Width 29, 30 Prescaler Field for Watchdog Timer 29, 30
C
Card Access Width 28 Card Detect 24 Card DMA Enable 27 Card Enable 28 Card Power Enable 24 Card Reset 28 Card Reset Output Enable 28 Card Write Protect 28 Chip ID 27 Count Field for Address and Data Setup Time 29, 30 Count Field for Command Strobe Width 29, 30 Count Field for Hold Period 29, 30 Count Field for Watchdog Timer 29, 30 CPU Initiated DMA 27 CPU Initiated DMA with Terminal Count 27
R
Report Read Failure 26 Revision Level 27
S
Standby Disable 24 Standby Request During Card Access 20, 24
D
Disable Protection for PCM_BVD[1] Input During Card Power Off 24 DMA Request Input Select 27 DMA Request Polarity Select 27 Dual/Single Socket 27
T
Timer Select for Attribute Space Read 28 Write 28 Timer Select for I/O Space Read 28 Write 28 Timer Select for Memory Space Read 28 Write 28 Transaction Queue Enable 26 Flush 26 Threshold Control 26 Transparent DMA Request 27
E
Enable Active pull-up on Open-Drain Interrupt Outputs PIRQ_L[1:0] 26 Enable Assembly and Disassembly 26 Enable Auto Idle Mode 24 Enable Handshake Using Card Rdy Signal 26 Enable Handshake with CL-PS7111 Using PDREQ_L 27 Endian Conversion Enable 26
G
GPIO Direction 25 GPIO Output Value When Card Power Enable Bit is High 25 Enable Bit is Low 25
V
VS[2:1] Direction 25 VS[2:1] Output Value 25
I
Idle 20, 21, 24 Input Pull-Up Enable 24 CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
November 1997
PRELIMINARY DATA BOOK v1.0
BIT INDEX
45
CL-PS6700
Low-Power PC Card Controller
INDEX
Numerics
100-pin VQFP package specifications 43 pin diagram 7
M
Memory bus 18 Memory or Register Write bus operation. See bus operations
A
abbreviations 5 absolute maximum ratings 33 acronyms 5
O
ordering information 44
P
PC Card access types 15 address spaces 18 address/data bus 18 byte assembly/disassembly 19 card types 18 configuration 19 DMA controller 18 hot insertion support 19 insertion 19 queueing 19 removal 19 PC Card (PCMCIA) Interface 18 PC Card Bus DMA Transaction bus operation. See bus operations PC Card Bus Read bus operation. See bus operations PC Card Bus Write bus operation. See bus operations pins alphabetical listing 8 description 10-17 diagram 7 ground and power 17 MD[15:0] 10, 10 numerical listing 9 PCE_L 12, 13, 14, 16, 17 PCLK 14 PCM_ IOWR_L 16 PCM_A[25:0] 14 PCM_BVD[2:1] 16 PCM_CD_L[2:1] 16 PCM_CE_L[2:1] 14 PCM_D[15:0] 14 PCM_IORD_L 16 PCM_OE_L 14 PCM_RDY 15 PCM_REG_L 15 PCM_RESET 17 PCM_VS[2:1] 17 PCM_WAIT_L 15 PCM_WE_L 14 PCM_WP 15
B
bus operations Memory or Register Write 38 PC Card Bus DMA Transaction 42 PC Card Bus Read 40 PC Card Bus Write 41 Register Read 38 Standby Mode Timing 42 System Bus Card Data Read 39
C
card read 12 card write 12 conventions abbreviations 5 acronyms 5 numbers and units 6
D
data buffering 18 DC specifications 34
E
electrical specifications 33 endianness conversion 18-19
F
functional description 18
I
I/O properties 31 interface signals Access Control 12-14, 16-17 Address/Data Bus 10 Interrupt and Abort 13, 16 PC Card 14 interrupt control 18
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
46
INDEX
PRELIMINARY DATA BOOK v1.0
November 1997
CL-PS6700
Low-Power PC Card Controller
pins (cont.) PCTL[2:0] 17 PDREQ_L/GPIO 13 PIRQ_L[1:0] 13, 16 PRDY 12 PSLEEP_L 13 PTYPE 12 RESET_L 13 power state active 20 idle 20 standby 20
registers (cont.) DMA control 27 Interrupt Clear 23 Interrupt Input Level 21, 23 Interrupt Mask 23 Interrupt Output Select 23 Interrupt Status 23 Power Management 20, 24 System Interface Configuration 26
S
Standby Mode Timing bus operation. See bus operations System Bus Card Data Read bus operation. See bus operations
R
register addresses 21 spacing 21 Register Read bus operation. See bus operations registers Card Interface Configuration 17, 28 Card Interface Timing Register 0A 29 Card Interface Timing Register 0B 29 Card Interface Timing Register 1A 30 Card Interface Timing Register 1B 30 Card Power Control 25 Device Information 27
T
timing PC Card bus 36 system bus 35
V
voltage translation 18
W
watchdog timer 19
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
November 1997
PRELIMINARY DATA BOOK v1.0
INDEX
47
CL-PS6700
Preliminary Data Book v1.0
Direct Sales Offices
Domestic
N. CALIFORNIA Fremont TEL: 510/623-8300 FAX: 510/252-6020 S. CALIFORNIA Westlake Village TEL: 805/371-5860 FAX: 805/371-5861 NORTHWESTERN AREA Portland, OR TEL: 503/620-5547 FAX: 503/620-5665 SOUTH CENTRAL AREA Austin, TX TEL: 512/255-0080 FAX: 512/255-0733 Irving, TX TEL: 972/252-6698 FAX: 972/252-5681 Houston, TX TEL: 281/257-2525 FAX: 281/257-2555 NORTHEASTERN AREA Andover, MA TEL: 978/794-9992 FAX: 978/794-9998 SOUTHEASTERN AREA Raleigh, NC TEL: 919/859-5210 FAX: 919/859-5334 Boca Raton, FL TEL: 561/241-2364 FAX: 561/241-7990
International
CHINA Beijing TEL: 86/10-6428-0783 FAX: 86/10-6428-0786 FRANCE Paris TEL: 33/1-48-12-2812 FAX: 33/1-48-12-2810 GERMANY Herrsching TEL: 49/81-52-92460 FAX: 49/81-52-924699 HONG KONG Tsimshatsui TEL: 852/2376-0801 FAX: 852/2375-1202 ITALY Milan TEL: 39/2-3360-5458 FAX: 39/2-3360-5426
JAPAN Tokyo TEL: 81/3-3340-9111 FAX: 81/3-3340-9120 KOREA Seoul TEL: 82/2-565-8561 FAX: 82/2-565-8565 SINGAPORE TEL: 65/743-4111 FAX: 65/742-4111 TAIWAN Taipei TEL: 886/2-718-4533 FAX: 886/2-718-4526 UNITED KINGDOM London, England TEL: 44/1727-872424 FAX: 44/1727-875919
High-Value `Systems in Silicon'
Headquartered in Fremont, California, Cirrus Logic is a leading manufacturer of advanced integrated circuits for the personal computer, consumer, and industrial markets. The Company's software-rich `systems in silicon' add high value to major brands worldwide in applications that span multimedia (graphics, audio, video), communications (enterprise networking and remote data access), and mass storage (magnetic and optical moving media). With a focus on innovative microperipheral chip solutions, Cirrus Logic is committed to technology leadership in the Interactive Age. Cirrus Logic's manufacturing strategy ensures maximum product quality and availability, as well as access to world-class processing technologies through joint ventures with IBM(R) and Lucent Technologies(R). Contact one of our systems and applications specialists to see how your company can benefit from the high value that Cirrus Logic adds to its customers' products. Copyright (c) 1997 Cirrus Logic, Inc. All rights reserved.
Preliminary product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system or transmitted in any form or by any means (electronic, mechanical, photographic, or otherwise) or used as the basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. Cirrus, Cirrus Logic, AccuPak, Alpine, Clear3D, Crystal, CrystalClear, CrystalWare, DirectVPM, DIVA, FastEn, FastPath, FasText, FeatureChips, FilterJet, Get into it, Good Data, IntelliFilter, Laguna, Laguna3D, Matterhorn, MediaDAC, Mojave, MotionVideo, MVA, SimulSCAN, S/LA, SmartAnalog, SMASH, SofTarget, SoundFusion, Stargate, Systems in Silicon, TextureJet, True-D, TVTap, UXART, VisualMedia, VPM, V-Port, V-Port Manager, Voyager, WavePort, and WebSet are trademarks of Cirrus Logic, Inc., which may be registered in some jurisdictions. Other trademarks in this document belong to their respective companies. CRUS and Cirrus Logic International, Ltd. are trade names of Cirrus Logic, Inc.
Cirrus Logic, Inc.
3100 West Warren Ave., Fremont, CA 94538 TEL: 510/623-8300 FAX: 510/252-6020
Publications Ordering: 800/359-6414 (USA) or 510/249-4200 Worldwide Web: http://www.cirrus.com
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